CMIS lane pages register map (10h, 11h, VDM, CDB)

Everything per lane in a CMIS module lives in banked pages: bank b (lower byte 126) covers lanes 8b+1 … 8b+8. Page 10h is where the host writes — data-path initialisation, Tx disable, polarity, squelch, equalisation and the staged control sets that select applications; page 11h is where it reads back — data-path states, per-lane flags, monitors, configuration status and the active control set. Pages 20h–2Fh hold VDM and 9Fh the CDB mailbox. This page lists the key bytes, compiled against CMIS 5.x (byte positions of some signal-integrity fields differ between 4.x and 5.x; those are given as ranges). Narrative: CMIS.

Legend: per-lane bytes use bit n−1 for lane n (bit 0 = lane 1 … bit 7 = lane 8); nibble fields use bits 7–4 for the odd lane and 3–0 for the even lane of each pair unless stated · rsvd = reserved.

Page 10h — lane control (host writes)

Byte	Field	Bits / contents
128	DPDeinitLane	bit per lane: 1 = deinitialise (take the lane's data path to DPDeactivated)
129	rsvd	—
130	OutputDisableTx	bit per lane: 1 = Tx output (laser) off
131	PolarityFlipTx	bit per lane: invert Tx electrical input
132	SquelchDisableTx	bit per lane: 1 = disable automatic Tx squelch
133	ForceSquelchTx	bit per lane: 1 = force Tx squelch
134	rsvd	—
135	AdaptiveInputEqEnableTx	bit per lane: 1 = adaptive host-side input equalisation
136	AdaptiveInputEqRecallTx	bit per lane: recall stored EQ setting (4.x: freeze)
137	rsvd	—
138–141	FixedInputEqTargetTx	nibble per lane (138: lanes 1–2 … 141: lanes 7–8): fixed input EQ code 0–15
142	rsvd	—
143	ApplyDPInitLane	bit per lane: 1 = apply Staged Control Set 0 and run DPInit
144	ApplyImmediateLane	bit per lane: apply SCS0 without re-initialising the data path
145–152	Staged Control Set 0 — data-path configuration	one byte per lane (145 = lane 1 … 152 = lane 8): bits 7–4 AppSelCode (1–15 = descriptor index, 0 = none) · 3–1 DataPathID (first host lane of the data path − 1) · 0 ExplicitControl (1 = use the SI settings below instead of the application defaults)
153	SCS0 AdaptiveInputEqEnableTx	bit per lane
154	SCS0 AdaptiveInputEqRecallTx	bit per lane
155	rsvd	—
156–159	SCS0 FixedInputEqTargetTx	nibble per lane
160	SCS0 CDREnableTx	bit per lane: 1 = Tx CDR on, 0 = bypass
161	SCS0 CDREnableRx	bit per lane
162–165	SCS0 OutputEqPreCursorTargetRx	nibble per lane
166–169	SCS0 OutputEqPostCursorTargetRx	nibble per lane
170–173	SCS0 OutputAmplitudeTargetRx	nibble per lane
174–177	rsvd	—
178–210	Staged Control Set 1	same layout as 145–177 (178–185 data-path configuration, 186–210 SI targets)
211–255	Rx output controls and masks	OutputDisableRx, PolarityFlipRx, SquelchDisableRx per lane; flag masks for page 11h (byte positions per revision)

Selection flow: write 145–152 → set 143 for the lanes → poll page 11h 202–205 for ConfigStatus → read 128–131 for the data-path state — CMIS, Speed & rate.

Page 11h — lane status (host reads)

Byte	Field	Bits / contents
128	DPStateHostLane 1–2	3–0 lane 1 state · 7–4 lane 2 state (code table below)
129	DPStateHostLane 3–4	as above
130	DPStateHostLane 5–6	—
131	DPStateHostLane 7–8	—
132–133	rsvd	—
134	DPStateChangedFlag	bit per lane; latched
135	TxFaultFlag	bit per lane
136	TxLOSFlag	bit per lane (host-side input LOS)
137	TxCDRLOLFlag	bit per lane
138	TxAdaptiveInputEqFailFlag	bit per lane
139	Tx power high alarm	bit per lane
140	Tx power low alarm	—
141	Tx power high warning	—
142	Tx power low warning	—
143	Tx bias high alarm	—
144	Tx bias low alarm	—
145	Tx bias high warning	—
146	Tx bias low warning	—
147	RxLOSFlag	bit per lane (media-side LOS)
148	RxCDRLOLFlag	bit per lane
149	Rx power high alarm	—
150	Rx power low alarm	—
151	Rx power high warning	—
152	Rx power low warning	—
153	OutputStatusRx	bit per lane: 1 = Rx output enabled/valid
154–169	Tx power monitors	2 bytes per lane (154–155 lane 1 … 168–169 lane 8), unsigned, 0.1 µW
170–185	Tx bias monitors	2 bytes per lane, 2 µA × multiplier
186–201	Rx power monitors	2 bytes per lane, 0.1 µW
202	ConfigStatus lanes 1–2	3–0 lane 1 · 7–4 lane 2 (code table below)
203	ConfigStatus lanes 3–4	—
204	ConfigStatus lanes 5–6	—
205	ConfigStatus lanes 7–8	—
206–213	Active Control Set — data-path configuration	one byte per lane, same layout as page 10h 145–152: the configuration actually in force
214–234	Active Control Set — SI settings	adaptive EQ enable/recall, fixed EQ, CDR Tx/Rx, Rx pre/post-cursor, Rx amplitude — mirror of the SCS layout
235	DPInitPending	bit per lane: 1 = a staged configuration awaits ApplyDPInit
236–255	rsvd / flags per revision	—

Data-path state codes (bytes 128–131)

Code	State	Meaning
1h	DPDeactivated	lane idle; Tx off
2h	DPInit	initialising with the applied configuration
3h	DPDeinit	tearing down
4h	DPActivated	Tx on, data flowing
5h	DPTxTurnOn	laser turning on
6h	DPTxTurnOff	laser turning off
7h	DPInitialized	configured, waiting for Tx enable
0h, 8h–Fh	rsvd	—

ConfigStatus codes (bytes 202–205)

Code	Status	Meaning
0h	ConfigUndefined	no configuration applied yet
1h	ConfigSuccess	staged set accepted and in force
2h	ConfigRejected	generic rejection
3h	ConfigRejectedInvalidAppSel	AppSel code not advertised
4h	ConfigRejectedInvalidDataPath	DataPathID not allowed for that application
5h	ConfigRejectedInvalidSI	signal-integrity target out of range
6h	ConfigRejectedLaneInUse	lane already part of another active data path
7h	ConfigRejectedPartialDataPath	not all lanes of the data path were configured
8h–Bh	rsvd	—
Ch	ConfigInProgress	applying
Dh–Fh	custom	vendor

Page 12h — tunable laser control (per lane)

Channel number set, wavelength/frequency set, fine-tuning offset, tuning status and flags per lane, with capabilities on page 04h — Tunable maps.

Pages 20h–2Fh — VDM (Versatile Diagnostics Monitoring)

Pages	Contents	Layout
20h–23h	Descriptors	2 bytes per observable (128–255 → 64 per page, 256 in total): byte 0 bits 7–4 threshold-set ID, 3–0 lane (0 = module-level); byte 1 observable type (1 laser age · 2 TEC current · 3 laser frequency error · 4 laser temperature · 5/6 eSNR media/host · 7/8 PAM4 level transition media/host · 9–16 pre-FEC BER min/max/avg/current media/host · 17–24 FERC min/max/avg/current media/host · 128+ coherent set)
24h–27h	Samples	2 bytes per observable, same index as its descriptor; formats U16 / S16 / F16
28h–2Bh	Thresholds	8 bytes per threshold set: high alarm, low alarm, high warning, low warning
2Ch–2Fh	Flags and masks	alarm/warning flags per observable (2Ch–2Dh) and masks (2Eh–2Fh)

F16 ratio format: bits 15–11 exponent e, bits 10–0 mantissa m; value = m × 10^(e − 24). Details: VDM & FEC metrics.

Page 9Fh — CDB command block

Bytes	Field	Contents
128–129	CMD ID	command identifier, MSB first (0000h query status · 0040h module features · 0041h firmware-management features · 0100h get firmware info · 0101h start firmware download · 0102h abort · 0103h write firmware block LPL · 0104h write firmware block EPL · 0107h complete download · 0109h run image · 010Ah commit image)
130–131	EPL length	bytes of extended payload in pages A0h–AFh
132	LPL length	bytes of local payload (0–120)
133	CdbChkCode	checksum over 128–132 and the LPL: one's complement of (Σ) mod 256
134	RPL length	reply payload length written by the module
135	RplChkCode	reply checksum
136–255	LPL	local payload (command parameters / reply)
A0h–AFh 128–255	EPL	up to 2048 bytes of extended payload

Writing byte 129 (the LSB of CMD ID) last triggers execution; the host then polls lower bytes 37–38 (CdbStatus) until CdbIsBusy clears.

CMIS lower page map — module state, flags, applications.
CMIS upper pages map — identity, advertising, thresholds.
SFF-8636 lower page map — the 4-lane predecessor.