SFF-8636 — QSFP management

SFF-8636, the Management Interface for Cabled Environments, is the management specification for the four-lane QSFP family — QSFP+ (40G), QSFP28 (100G) and most QSFP56 (200G) modules — and for related parallel form factors such as CXP and microQSFP. It succeeded SFF-8436, kept its memory layout, and keeps growing through revisions 2.x. Fibre Channel and InfiniBand QSFP modules use it too. Version byte and revision history: Specification revisions.

One address, paged memory

Unlike SFP's two devices, a QSFP module answers at a single address (A0h) over the two-wire interface:

Lower page 00h (bytes 0–127) is always visible: status, interrupt flags, live monitors, controls, and the page-select byte 127.
Upper pages (bytes 128–255) are swapped in by writing 127: page 00h identity, 01h application select table, 02h user EEPROM, 03h thresholds and channel controls, optional 20h–21h.

Modules with only page 00h set the flat memory bit (byte 2 bit 2). A multi-module host bus is arbitrated by the ModSelL pin, not by address. Bus speed up to 400 kHz is allowed from revision 2.x.

Lower page 00h — status and control

Bytes	Block	Notes
0	Identifier	0Dh QSFP+, 11h QSFP28 (SFF-8024)
1	Revision compliance	which SFF-8436/8636 revision the map follows
2	Status	bit 2 flat memory, bit 1 IntL asserted, bit 0 data not ready
3–21	Interrupt flags	3 Rx/Tx LOS per lane, 4 Tx fault, 5 Tx/Rx LOL (CDR lock), 6 temperature alarms/warnings, 7 Vcc, 9–10 Rx power, 11–12 Tx bias, 13–14 Tx power; latched, cleared on read
22–33	Module monitors	temperature (22–23), Vcc (26–27); same formats as SFP
34–81	Channel monitors	Rx power lanes 1–4 (34–41), Tx bias (42–49), Tx power (50–57), reserved/vendor to 81 — per-lane diagnostics
86	Tx disable	bits 0–3, one per lane
87–88	Rate select	Rx (87) and Tx (88), two bits per lane — rate select
89–92, 94–97	Application select	per lane, indexes into page 01h
93	Power control	bit 0 power override, bit 1 power set (1 = low power), bit 2 enable classes 5–7, bit 3 enable class 8
98	CDR control	bits 7–4 Tx CDR on per lane, 3–0 Rx CDR on — CDR
100–106	Interrupt masks	one mask bit per flag
107	Max power	×0.1 W, for class 8 modules (rev 2.10)
119–122	Password change	vendor-defined
123–126	Password entry	vendor-defined — the usual place for the write-protection password
127	Page select	write before reading 128–255

Upper page 00h — identity

Bytes	Field	Notes
128	Identifier	repeats byte 0
129	Extended identifier	bits 7–6 power class 1–4, bit 5 class 8 declared, bit 4 CLEI present, bit 3 Tx CDR present, bit 2 Rx CDR present, bits 1–0 power class 5–7
130	Connector	0Ch MPO 1×12, 07h LC, 23h no separable connector (DAC/AOC)
131–138	Specification compliance	131 Ethernet 10/40G (bit 7 = use byte 192), 132 SONET, 133 SAS/SATA, 134 GbE, 135–138 Fibre Channel — Compliance codes
139	Encoding	05h 64B/66B, 08h PAM4 (note: values differ from SFP's table)
140	Nominal bit rate	×100 Mb/s per lane; FFh → see byte 222
141	Extended rate select	—
142–146	Link lengths	SMF km, OM3 ×2 m, OM2 m, OM1 m, copper metres or OM4 ×2 m
147	Device technology	transmitter type nibble (below) + wavelength control, cooled, APD/PIN, tunable bits
148–163	Vendor name	16 ASCII — Vendor fields
164	Extended module	InfiniBand rate bits (SDR…EDR)
165–167	Vendor OUI	—
168–183	Vendor PN	—
184–185	Vendor rev	2 ASCII
186–189	Wavelength & tolerance	×0.05 nm and ×0.005 nm; for copper: attenuation at 2.5 / 5 / 7 / 12.9 GHz
190	Max case temperature	°C
191	CC_BASE	checksum of 128–190 — Checksums
192	Extended compliance	SFF-8024 Table 4-4 code (100GBASE-SR4 = 02h, CWDM4 = 06h…)
193–195	Options	equalisation/emphasis controls, CDR on/off and LOL flags, squelch, which pages are provided
196–211	Vendor SN	—
212–219	Date code	YYMMDD + 2 lot
220	Diagnostic monitoring type	Rx power average/OMA, Tx power monitor implemented
221	Enhanced options	initialisation-complete flag, rate-select declaration, Tx-disable fast mode
222	Extended bit rate	×250 Mb/s when byte 140 = FFh
223	CC_EXT	checksum of 192–222
224–255	Vendor specific	—

Byte 147 — transmitter technology (bits 7–4)

Value	Technology	Value	Technology
0h	850 nm VCSEL	8h	other / undefined
1h	1310 nm VCSEL	9h	1490 nm DFB
2h	1550 nm VCSEL	Ah	copper, unequalised
3h	1310 nm FP	Bh	copper, passive equalised
4h	1310 nm DFB	Ch	copper, near & far end limiting active
5h	1550 nm DFB	Dh	copper, far end limiting active
6h	1310 nm EML	Eh	copper, near end limiting active
7h	1550 nm EML	Fh	copper, linear active equalisers

Bits 3–0: wavelength control, cooled transmitter, APD (1) vs PIN (0) detector, tunable. What these technologies are: Lasers.

Other pages

Page	Contents
01h	application select table (AST) — advertised applications for SFF-8079-style selection; rarely used
02h	user EEPROM (128–255); CLEI code when byte 129 bit 4 is set
03h	thresholds: module 128–175 (temperature, Vcc), channel 176–223 (Rx power, Tx bias, Tx power); channel controls 226–241 (Tx input equalisation, Rx output emphasis and amplitude, squelch and output disable); channel monitor masks 242–253
20h–21h	optional extended functions, declared in byte 195 bit 0

Threshold semantics: Thresholds & alarms.

Power classes

Byte 129 declares the class, byte 93 lets the host release the module from low power and enable classes 5–8, byte 107 gives the exact maximum for class 8. A host that reads a class its port cannot supply keeps the module in low power — the Power & thermal material lists the classes and symptoms.

Interrupts and LOL

IntL goes low when any unmasked flag in bytes 3–21 is set; the host reads the flags, which clears them. The LOL flags (byte 5) are the CDR's lock indicator and the quickest sign of a rate mismatch — see Speed & rate.

What hosts read

Insertion → wait for data-ready → read lower 0–127 and upper 00h → verify CC_BASE / CC_EXT → decode identifier, connector, compliance and byte 192, vendor block → check power class → release low power → configure CDR/rate → clear Tx disable → poll monitors and flags. Sequence and timings: What the host does.

In CodingBox

CodingBox reads all present pages, shows them as tabs in the EEPROM editor with every field named, decodes byte 147 and the compliance bytes on Check transceiver, plots the four lanes on DDM and recalculates CC_BASE and CC_EXT on write.

Full register tables: Lower page 00h map (flags, monitors, controls) and Upper pages map (identity, thresholds, channel controls).