QSFP112

QSFP112 brings 400 Gb/s into the four-lane QSFP outline by running each lane at 100G PAM4. It gives switch makers a 400G port that is mechanically a QSFP — smaller and cooler than an eight-lane QSFP-DD at the same total rate — at the cost of needing the most advanced 100G-per-lane electronics.

Key facts


Lanes × rate	4 × 106.25 Gb/s (PAM4)
Total	400G
Connector	MPO-12 (DR4/SR4), LC duplex (FR4/LR4), DAC/AOC
Supply	3.3 V, high power class (module and host thermal design critical)
Applications	400GBASE-DR4/FR4/LR4/SR4 (IEEE 802.3ck/df), InfiniBand NDR, 4×100G breakout

Specifications

QSFP112 MSA hardware specification — mechanical outline (QSFP28/56 compatible),

the 112 Gb/s-per-lane connector and cage requirements, thermal.

Electrical: 400GAUI-4 (IEEE 802.3ck) — four 100G PAM4 lanes.
Management: CMIS — see CMIS.

Management interface

QSFP112 is a CMIS-only form factor. The module exposes CMIS lower memory (state, flags, controls) and banked upper pages for identity, application advertisement, per-lane data-path control and diagnostics. The host drives the module through the CMIS state machine — low power → high power → data path activation — and selects an application (host/media interface pair) before the link trains. Identity and interface codes come from SFF-8024.

Compatibility notes

Accepts QSFP56, QSFP28 and QSFP+ modules at their rates.
4×100G breakout to four 100G single-lane links (e.g. SFP112-class or DR4 fan-out).
Fits a QSFP-DD cage on four of eight lanes; a QSFP-DD800 host may run a QSFP112 at 400G.

In CodingBox

CodingBox reads QSFP112 with the CMIS decoder — module state, identity, applications and per-lane diagnostics appear in the EEPROM editor and DDM screen. For CMIS-specific bring-up problems see CMIS issues.